1. Field of the Invention
The present invention relates to a digital-to-analog converter for converting a digital signal to an analog signal, and relates to its method.
2. Description of the Related Art
There is known a digital-to-analog converter of a pulse width modulation (PWM) system. This type of digital-to-analog converter inputs a pulse signal, which is pulse-width modulated in accordance with a digital value, to a low-pass filter, and converts it to an analog value. There is also known a digital-to-analog converter of a pulse density modulation (PDM) system. This type of digital-to-analog converter inputs a pulse signal, which is pulse-density modulated in accordance with a digital value, to a low-pass filter, and converts it to an analog value.
In either of these digital-to-analog converters, a response speed (digital/analog converting speed) depends on a time constant of the low-pass filter.
FIG. 1 is a functional block diagram of a conventional digital-to-analog converter of a PWM system. The digital-to-analog converter shown in FIG. 1 comprises a PWM signal generating section 103 having a counter 101 and a comparator 102, and a low-pass filter 104.
The counter 101 cyclically counts a count value 105 having the same number of bits as the number of set bits of a D/A conversion, and outputs the count value 105 to the comparator 102.
The comparator 102 compares the count value 105 with a set digital value 106, and outputs a PWM signal 107 to the low-pass filter 104. More specifically, the comparator 102 pulse-width modulates the set digital value 106 using the count value 105 (a duty ratio is varied). The pulse signal, which is obtained by pulse-width modulating the set digital value 106, is the PWM signal 107.
The low-pass filter 104 removes a high frequency component of the PWM signal 107, thereby outputting a voltage value corresponding to the set digital value 106, that is, an analog signal 108.
The above digital-to-analog converter of a PWM system has an advantage in which a circuit scale is smaller than a general digital-to-analog converter of a resistance array type.
However, in the above digital-to-analog converter of a PWM system, the response speed depends on the time constant of the low-pass filter 104. In order to realize the same degree of the response speed as the general digital-to-analog converter of a resistance array type, the operation frequency of the counter 101 provided in the PWM signal generating section 103 must be more increased, and this increases a consumption current.
An object of the present invention is to provide a digital-to-analog converter, which can realize a high response speed as operating a counter at low speed to a minimum so as to reduce a consumption current, and its method.
The present invention provides a digital-to-analog converter comprising:
a pulse-width modulator for pulse-width modulating an actual set value using a count value so as to generate a pulse-width modulation signal;
a low-pass filter for removing a high frequency component of the pulse-width modulation signal so as to output an analog signal; and
an actual set value calculator for multiplying a difference between a current target set value and a previous target set value by a coefficient determined from a time constant of the low-pass filter and a cycle of the target set value, and for adding the multiplied value to the previous target set value so as to calculate the actual set value.
According to the above-structured digital-to-analog converter, the pulse-width modulation is performed using the actual set value, which can bring about a variation, which is larger than a target digital value in a unit time, to the analog output value of the low-pass filter. The analog signal, which is the analog output of the low-pass filter, can be varied at higher speed. As a result, it is unnecessary to perform the pulse-width modulation with the count value of the operation frequency that is more than necessary. This can reduce the consumption current.
Also, the present invention provides a digital-to-analog converter comprising a pulse-density modulator, in place of the pulse-width modulator, for reversing upper and lower bits of the count value so as to pulse-density modulate the actual set value with the reversed count value and to be output to the low-pass filter.
According to the above-structured digital-to-analog converter, the analog signal having high stability and a small number of ripples can be generated as compared with the pulse-width modulator.
Moreover, the present invention provides a digital-to-analog converter comprising an coefficient setting function for changing the coefficient by which the difference between the target set value and the previous target set value are multiplied in accordance with a polarity of the difference.
According to the above-structured digital-to-analog converter, since the response speed can be accurately adjusted by the positive and negative changes, it is possible to realize the high-speed response using the low-speed operation frequency, thereby making it possible to reduce the consumption current.
Furthermore, the present invention provides a digital-to-analog converter comprising:
a determining section for determining whether or not the actual set value exceeds a set capable range; and
a selecting section for selecting the current target set value as the actual set value when the actual set value exceeds the set capable range as a result of the determination.
According to the above-structured digital-to-analog converter, the A/D conversion processing in the vicinity of the maximum value of the set capable range and the minimum value thereof can be executed without having a complicated processing. In other words, the A/D conversion processing can be accurately executed without increasing the consumption current.
Also, the present invention provides a digital-to-analog converter comprising:
a determining section for determining whether or not the actual set value exceeds a set capable range; and
a correcting section for prolonging a set cycle to lessen the coefficient by which the difference between the set target set value and the previous target set value are multiplied so as to calculate the actual set value cycle when the actual set value exceeds the set capable range as a result of the determination.
According to the above-structured digital-to-analog converter, the analog signal can be generated at higher speed even in the vicinity of the maximum value of the set capable range and the minimum value thereof. Therefore, the PWM or PDM signal generating function can be operated at low speed in the entire set capable range, thereby making it possible to improve the reduction in consumption current.